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On April 1st 2003 the following semiconductor operations were transferred to Renesas Technology Corporation: operations covering microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.). Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have all been changed to Renesas Technology Corporation. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Thank you for your understanding. Renesas Technology Home Page: www.renesas.com
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--PRELIMINARY--
HD66775
120-Channel Gate Driver for Color-TFT Liquid Crystal Displays
Rev.0.3 September 2001 Description
HD66775 is a gate-driver IC for systems with color-TFT-liquid-crystal dot-matrix graphic displays. It incorporates a circuit for driving 120 channels of TFT gate lines, and realizes the liquid crystal display. When two HD66775s are used with the HD66770 396-channel source driver with on-chip RAM and the HD667P00 power-supply IC chip, and used with the HD66772 528-channel source driver with onchip RAM and the HD667P00 power-supply IC chip, this LSI is suitable for color TFT displays of cellular phones having 132-by-176 and 176-by-240 dots, respectively.
Features
* TFT gate-line driving circuits 120 outputs: can be expanded to 240 channels with the master/slave function (two HD66775s are used) * Gate-line scanning Centering-screen function (vertically separated, comb type) * Mode setting Serial transfer from the HD66770/772 source driver * Power-supply voltage Logic power supply: Vcc - GND = 1.8 to 3.3 V Power supply for a gate-line driving circuit: VGH - VGL = 18 to 33 V (GND reference voltage: 9 to 16.5 V) Power supply for driving a gate line: VGH - GND = 9 to 16.5 V, and Vgoff - GND = -5 to -16.5 V * Power-supply circuit Each power-supply voltage is supplied from the HD667P00 power-supply IC chip.
HD66775
Type Number
Type Number HCD66775BP External Appearance Die with Au bump
2
HD66775
Pin Functions
Table 1 Pin Functions
Signal Name*1 Vcc1/Vcc2 GND1/GND2 VGH1/VGH2 Quantity*2 2 2 2 Input/ Output Connected to Power supply Power supply HD667P00 Function VCC-GND: A logic-circuit power supply. Supply the same voltage as that for HD66770/772 and HD667P00. A power supply for the gate-line driving circuit and a positive-side power supply for TFT-gate on level. A power supply for the gate-line driving circuit and a negative-side power supply. A power supply for driving the gate line at the TFT-gate off level. The reset pin. When a low level is input here, the LSI is initialized. Be sure to apply a signal to this pin during the system's power-on reset. RESET1* and RESET2* are equivalent inputs. Supply the reset signal to either, and leave the other open. Clock input pin supplied from HD66770/772. Gate line output changes at the falling edge of this signal. Performs frame synchronization with the source driver. Operates as a clock for the transfer of register settings. Latches data on the rising edge of the clock. Operates as the data for the transfer of register settings. A chip-select signal. Low: selected (data-transfer enabled), high: not selected (data-transfer disabled) Display-off signal. This signal becomes valid asynchronously with the FLM and CL1. High: Normal output; Low: All output Vgoff. Input for selecting the master or slave. Must be fixed to Vcc for the input of the LSI that scans the first line. Input for selecting the scan mode. Must be fixed to Vcc or GND depending on the selected scan mode. An output signal to the gate line. Outputs VGH as the gate-line selection level, or Vgoff as the gate-line non-selection level.
VGL1/VGL2 Vgoff1/Vgoff2 RESET1*/ RESET2*
2 2 2
Input
HD667P00 HD667P00 External reset circuit
CL11/CL12
2
Input
CL1 of HD66770/772 FLM of HD66770/772 GCL of HD66770/772 GDA of HD66770/772 GCS* of HD66770/772 DISPTMG of HD66770/772 Vcc or GND
FLM1/FLM2 GCL1/GCL2
2 2
Input Input
GDA1/GDA2 GCS1*/GCS2 * DISPTMG1/ DISPTMG2 MS
2 2
Input Input
2
Input
1
Input
SCM
1
Input
Vcc or GND
G1-G120
120
Output
Liquid crystal output
3
HD66775
Table 1 Pin Functions (cont)
Signal Name*1 GTEST1, GTEST2 Quantity*2 2 Input/ Output Output Connected to Liquid crystal output or open Function Dummy gate output. When CAD bit is high, output VGH and Vgoff level. When CAD bit is low, output Vgoff level. When these pins are not used, leave them open.
Notes: 1. Signal names 1/2 are equivalent inputs. Supply the reset signal to either, and leave the other open. 2. The quantity does not match the number of pads.
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HD66775
HCD66775BP Pad Arrangement
5
HD66775
HCD66775BP Pad Coordinates
The pad coordinates are shown below. The pad numbers in the pad arrangement correspond to the numbers in the following table that lists the pad center coordinates with the chip-centered origin.
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HD66775
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Pin Name DUMMY1 DUMMYR1 DUMMYR2 DUMMYR3 DUMMYR4 iDUMMY1 iDUMMY2 iDUMMY3 iDUMMY4 iDUMMY5 iDUMMY6 iDUMMY7 iDUMMY8 iDUMMY9 iDUMMY10 iDUMMY11 iDUMMY12 iDUMMY13 iDUMMY14 iDUMMY15 iDUMMY16 iDUMMY17 iDUMMY18 iDUMMY19 iDUMMY20 iDUMMY21 iDUMMY22 iDUMMY23 iDUMMY24 iDUMMY25 iDUMMY26 iDUMMY27 iDUMMY28 iDUMMY29 iDUMMY30 iDUMMY31 DUMMYR5 DUMMYR6 DUMMYR7 DUMMYR8 DUMMY2 Vcc1 SCM GND1 VGL1 Vgoff1 VGH1 RESET1* DISPTMG1 CL11 FLM1 GDA1 GCS1* GCL1 GTEST1 G1 G2 G3 G4 G5
X (um) -2215 -2080 -2015 -1950 -1885 -1800 -1680 -1560 -1440 -1320 -1200 -1080 -960 -840 -720 -600 -480 -360 -240 -120 0 120 240 360 480 600 720 840 960 1080 1200 1320 1440 1560 1680 1800 1885 1950 2015 2080 2215 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5 2202.5
Y (um) -1370 -1357.5 -1357.5 -1357.5 -1357.5 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1355 -1357.5 -1357.5 -1357.5 -1357.5 -1370 -1267.5 -1184.5 -1101.5 -871.5 -691.5 -301.5 -86.5 -16.5 53.5 123.5 193.5 263.5 333.5 561 626 691 756 821 886
No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pin Name G6 G7 DUMMY3 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 G44 G45 G46 G47 G48 G49 G50 G51 G52 G53 G54 G55 G56 G57 G58 G59 G60 G61 G62 G63 G64
X (um) 2202.5 2202.5 2215 2100 2060 2020 1980 1940 1900 1860 1820 1780 1740 1700 1660 1620 1580 1540 1500 1460 1420 1380 1340 1300 1260 1220 1180 1140 1100 1060 1020 980 940 900 860 820 780 740 700 660 620 580 540 500 460 420 380 340 300 260 220 180 140 100 60 20 -20 -60 -100 -140
Y (um) 951 1016 1370 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5
No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Pin Name G65 G66 G67 G68 G69 G70 G71 G72 G73 G74 G75 G76 G77 G78 G79 G80 G81 G82 G83 G84 G85 G86 G87 G88 G89 G90 G91 G92 G93 G94 G95 G96 G97 G98 G99 G100 G101 G102 G103 G104 G105 G106 G107 G108 G109 G110 G111 G112 G113 DUMMY4 G114 G115 G116 G117 G118 G119 G120 GTEST2 GCL2 GCS2*
X (um) -180 -220 -260 -300 -340 -380 -420 -460 -500 -540 -580 -620 -660 -700 -740 -780 -820 -860 -900 -940 -980 -1020 -1060 -1100 -1140 -1180 -1220 -1260 -1300 -1340 -1380 -1420 -1460 -1500 -1540 -1580 -1620 -1660 -1700 -1740 -1780 -1820 -1860 -1900 -1940 -1980 -2020 -2060 -2100 -2215 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5
Y (um) 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1227.5 1357.5 1370 1016 951 886 821 756 691 626 561 333.5 263.5
7
HD66775
No. Pin Name 181 GDA2 182 FLM2 183 CL12 184 DISPTMG2 185 RESET2* 186 VGH2 187 Vgoff2 188 VGL2 189 GND2 190 MS 191 Vcc2
X (um) -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5 -2202.5
Y (um) 193.5 123.5 53.5 -16.5 -86.5 -301.5 -691.5 -871.5 -1101.5 -1184.5 -1267.5
No. -
Pin Name TG1 TG2
X (um) -1970 1970
Y (um) -1185 -1185
8
HD66775
Internal Block Diagram
Figure 1 Block Diagram
Block Functions
1. Interface circuit Transfers data to the internal control register. 2. Scan data generation circuit Selects the output of the gate line one by one according to the FLM signal and the setting of the internal control registers. 3. Level shifter Converts the level of the operating power supply voltage Vcc - GND of the logic circuit to the level of the operating power supply voltage VGH - VGL of the gate-line driving circuit. 4. Gate-line driving circuit Selects and outputs either the VGH or the Vgoff level according to the selection signal generated at the scan data generation circuit and the level shifter.
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HD66775
Instructions
Outline HD66775 has three internal registers. The data is written on to these registers by using a gate serial data interface. This interface can be directly connected to the HD66770 or HD66772 source driver for an automatic transfer of instructions. When an instruction is written on to HD66770/772 via the bus from the CPU, it is output from the serial interface of HD66770/772, and HD66775 receives the instruction to adjust the settings of one of its internal registers. When the display system uses two HD66775s, the same instructions are transferred to both. Both HD66775s use the master/slave function to scan the gate line as well the LSI in this case is scanned. In the bit configuration for the transfer of instructions, the upper three bits are index numbers that indicate the target register of the transfer, and the lower 13 bits are the data. This interface is common for HD66775 and HD667P00. Index numbers R00h to R02h are instructions for HD667P00, SLP and GON of R00h, and numbers R06h to R07h are instructions for HD66775. Detailed Description Display-Off Control (R00h) Output Start-Position Control and Number of Valid Lines Control (R06h) Output Scan-Direction Control and Output Scan-Method Control (R07h)
Figure 2 R06h and R07h Instructions SLP: When SLP = 1, the HD66775 is in the sleep mode. G1 to G120 and GTEST1 and GTEST2 are output as GND. However, the register settings are kept. For details, refer to the target specifications of the HD66770/772. GON: When GON = 0 and DISPTMG = 0, G1 to G120 and GTEST1 and GTEST2 are output as GND. When GON = 1, G1 to G120 are normally output. For the display on/off flow, refer to the section of the instruction setting flow of the HD66770/772.
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HD66775
CAD: When CAD is low, GTEST1 and GTEST2 output Vgoff level. When CAD is high, GTEST1 and GTEST2 output VGH/Vgoff levels in the timing which is shown in figure 3. GS: Selects the output scan direction of the gate driver. For description on the GS value and the scan direction, refer to the section of master/slave function and scan mode setting. SCN4-0: Set the output start position. According to the correspondence between the setting values and the output start position in table 2, start driving the gate line by the gate line selection circuit. NL4-0: Set the number of valid lines from the output start position. According to the correspondence between the setting values and the valid lines in table 3, drive the gate line for the number of valid lines using the gate-line selection circuit. Set the NL4-0 and SCN4-0 so that (output start position + number of valid lines) - 1 240 lines. FLD1-0: Set the number of valid lines to drive n-line interlacing. Table 4 shows the correspondence between the setting value and the number of fields. Table 5 shows the scan method. The numbers in circles indicate the scanning order.
Figure 3 Output Timing for GTEST1 and GTEST2
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HD66775
Table 2 Correspondence between SCN4-0 and Output Start Position
Output Start Position SCM1 = GND SCM2 = GND SCN 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 G1 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G113 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G120 G112 G104 G96 G88 G80 G72 G64 G56 G48 G40 G32 G24 G16 G8 G1 G9 G17 G25 G33 G41 G49 G57 G65 G73 G81 G89 G97 G105 G1 G5 G9 G13 G17 G21 G25 G29 G33 G37 G41 G45 G49 G53 G57 G61 G65 G69 G73 G77 G81 G85 G89 G93 G97 G101 G105 G109 G113 G120 G116 G112 G108 G104 G100 G96 G92 G88 G84 G80 G76 G72 G68 G64 G60 G56 G52 G48 G44 G40 G36 G32 G28 G24 G20 G16 G12 G8 SCN3 SCN2 SCN1 SCN0 GS = 0 SCM1 = GND SCM2 = GND GS = 1 SCM1 = Vcc SCM2 = GND GS = 0 SCM1 = Vcc SCM2 = GND GS = 1 SCM1 = Vcc SCM2 = Vcc GS = 0 SCM1 = Vcc SCM2 = Vcc GS = 1
Note: When the LSI is set as MS = GND or SCM = Vcc, an output is not started.
12
HD66775
Table 3 Correspondence between NL4-0 and the Number of Valid Lines
NL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 NL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 NL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 NL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Number of Valid Lines Setting inhibited 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 208 216 224 232 240
Table 4 Correspondence between FLD1-0 and N-Line Interlacing Scan
FLD1 0 0 1 1 FLD0 0 1 0 1 Scan Method Setting inhibited One field Setting inhibited Three fields
13
HD66775
Table 5 N-Line Interlacing Scan Method
Note:
The numbers in circles indicate the scanning order.
14
HD66775
Master/Slave Function and Scan Mode Setting
The master/slave function uses two HD66775s for the 240-output gate driver function. Fix the MS pin of the driver that scans the first line to the Vcc level, and MS pin of the other driver to GND. Shift direction of the gate signal can be changed by setting the input levels of the SCM pin and the GS bit. Using the master/slave function with the shift direction enables various types of connections between the liquid crystal display panel and the HD66775. For details, refer to table 6, Master/Slave and Scan Mode Settings.
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HD66775
Table 6 Master/Slave and Scan Mode Settings
16
HD66775
Gate Serial Transfer
The register settings are transferred from HD66770 or HD66772. The interface consists of a chip select (GCS*), a transfer clock (GCL), and data input (GDA) lines. The data transfer starts when the falling edge of the GCS* line indicates that the data is to be transferred. The transfer ends when the rising edge of the GCS* line indicates that the transfer is over. The bits are transferred in 16-bit units, and the data is transferred in the order from MSB to LSB.
Figure 4 Format for Data Transfer
Reset Functions
HD66775 sets the internal initialization with the RESET pin. Input a power-on reset signal when the power is applied as in the case with HD66770, HD66772, or HD667P00. Table 7 shows the initial setting values. Table 7 Initial Setting Values for Registers at Reset
Index Code R00h R01h R06h Control Bit SLP GON CAD SCN4-0 NL4-0 GS R07h FLD1-0 Initial Value 0 0 0 00000 11101 0 01 Status Cancels sleep mode. Gate output control for display off: GND GTEST1 and GTEST2 output Vgoff only Output start position: G1 Number of valid lines: 240 Scan direction control: G1-G120 N-line interlacing control: normal scan
17
HD66775
Interface between the Liquid Crystal Display Panel
Figures 5 to 8 show the connection example for the configuration of the 176-dot-row TFT-LCD panel using two HD66775s, and SCN, NL, and GS bit settings and the scanning range of gate lines.
Figure 5 Connection Example (1)
18
HD66775
Figure 6 Connection Example (2)
Figure 7 Connection Example (3)
19
HD66775
Figure 8 Connection Example (4)
20
HD66775
Example of System Configuration
Figure 9 shows a TFT-LCD panel with 132 (horizontal)-by-176 (vertical) dots, configured by using the HD66770 source driver and the HD667P00 power-supply chip.
Figure 9 System Configuration
21
HD66775
Example of Connection to HD66770 and HD667P00
Connection differs according to the voltage setting of Vcom. Figure 10 shows an example of connection to HD66770 source driver and HD667P00 power-supply IC when VcomL < 0 V and 0 V VcomL < 5.5 V.
22
HD66775
Notes:
1. 2.
All Vcc and GND input to HD66770, HD66775, and HD667P00 must be the same. Leave the EQ and Vcom pins of HD66770 open. Set the EQ pin of HD667P00 to GND. 3. Use the 1-F capacitor (B characteristics) as a capacitor for stabilization to be connected. 4. There is no description of how to connect the capacitors of C11- to C12-, C11+ to C12+, C21- to C23-, C21+ to C23+, C31-, C31+, C41-, and C41+ of HD667P00. Connect these capacitors according to the HD667P00 pin functions. 5. Apply 2.5 to 3.3 V to Vci by using an external power supply, and connect VciOUT to Vci1 or apply 2.75 V or lower to Vci1 by using an external power supply. Apply 2.5 to 3.3 V or lower to Vci4 by using an external power supply. 6. Conncet the Shottky barrier diode when VF = 0.4 V/20 mA and VR 30 V. 7. Use the 0.1-F capacitor (B characteristics) as a capacitor for stabilization to be connected. 8. Connect the 0.1-F capacitor (B characteristics) as a capacitor for stabilization according to the display quality and power consumption. 9. When step-up circuit 4, VcomL, and VgoffH are used, use the 1-F capacitor (B characteristics) according to the setting mode. When they are not used, leave the pin open. 10. Use 200-k or higher variable resistor.
Figure 10 Example of Connection to HD66770 and HD667P00 when VcomL < 0 V
23
HD66775
Figure 11 shows an example of connection to HD66770 source driver and HD667P00 power-supply IC when 0 VcomL < 5.5 V.
Notes:
All Vcc and GND input to HD66770, HD66775, and HD667P00 must be the same. Connect the EQ pins of HD66770 and HD667P00. The Vcom pin must be connected to the Vcom pin of HD667P00. Do not set the Vcom voltage higher than 5.5 V. 3. Use the 1-F capacitor (B characteristics) as a capacitor for stabilization to be connected. 4. There is no description of how to connect the capacitors of C11- to C12-, C11+ to C12+, C21- to C23-, C21+ to C23+, C31-, C31+, C41-, and C41+ of HD667P00. Connect these capacitors according to the HD667P00 pin functions. 5. Apply 2.5 to 3.3 V to Vci by using an external power supply, and connect VciOUT to Vci1 or apply 2.75 V or lower to Vci1 by using an external power supply. Apply 2.5 to 3.3 V or lower to Vci4 by using an external power supply. 6. Conncet the Shottky barrier diode when VF = 0.4 V/20 mA and VR 30 V. 7. Use the 0.1-F capacitor (B characteristics) as a capacitor for stabilization to be connected. 8. Connect the 0.1-F capacitor (B characteristics) as a capacitor for stabilization according to the display quality and power consumption. 9. When step-up circuit 4, VcomL, and VgoffH are used, use the 1-F capacitor (B characteristics) according to the setting mode. When they are not used, leave the pin open. 10. Use 200-k or higher variable resistor.
1. 2.
Figure 11 Example of Connection to HD66770 and HD667P00 when 0 V VcomL < 5.5 V
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HD66775
Absolute Maximum Ratings
Item Power supply voltage Logic circuit LCD drive circuit Input voltage Operating temperature Storage temperature Symbol Vcc VGH - GND VGL - GND VT1 topr Tstg Ratings -0.3 to +4.6 -0.3 to +17.5 -17.5 to +0.3 -0.3 to Vcc + 0.3 -40 to +85 -55 to +110 Unit V V V V C C 1, 2 Notes 1
Notes: 1. Voltage from GND. 2. Applies to the CL1, FLM, GCS*, GDA, GCL, RESET*, DISPTMG, MS, and SCM pins.
Note: If the LSI is used beyond the above maximum ratings, it may be permanently damaged. It should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability.
25
HD66775
Electrical Characteristics
DC Characteristics (VCC = 1.8 to 3.3 V, VGH - VGL = 18 to 33 V, GND = 0 V, Ta = -40 to +85C)*1
Item Input high voltage Input low voltage Driver on resistance Driver on resistance Input leakage current Operating frequency Current consumption 1 Symbol VIH VIL RONH RONL IIL fopr Icc 1/240 duty, 60-Hz frame frequency, VCC = 3 V, VGH - VGL = 33 V 1/240 duty, 60-Hz frame frequency, VCC = 3 V, VGH - VGL = 33 V VGH - VGL = 33 V, Iload = 100 A VGH - VGL = 33 V, Iload = 100 A Vin = 0 to VCC Test Condition min. 0.8 x Vcc 0 -2.5 10 typ. max. Vcc 0.2 x Vcc 10 10 2.5 100 T.B.D. Unit V V k k A kHz A 4 Notes 2 2 3 3 2
Current consumption 2
IGH
T.B.D.
A
4
Notes: 1. For electrical characteristics of the product shipped with the chip, guaranteed at 85C. 2. Applies to the CL1, FLM, GCS*, GDA, GCL, RESET*, DISPTMG, MS, and SCM pins. 3. Resistance values between the G and V pins (VGH or Vgoff) when the load current flows one of G1 to G120 pins. The following condition is specified. G1 to G120 pins that are not measured are left open. VGH = +16.5 V, Vgoff = -16.5 V, Iload = 100 A 4. The output pins are not loaded.
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HD66775
AC Characteristics (VCC = 1.8 to 3.3 V, VGH - VGL = 18 to 33 V)
Item CL1 high-level width CL1 low-level width CL1 cycle time CL1/GCL rising time CL1/GCL falling time FLM setup time FLM hold time GCL cycle time CCL high-level width CCL low-level width GDA setup time GDA hold time GCS low setup time GCS high hold time Output delay time Symbol tCWH tCWL tCYC tr tf tFS tFH tcycG tCWHG tCWLG tGDS tGDH tGSL tGHH tDD Pin CL1 CL1 CL1 CL1 CL1 FLM, CL1 FLM, CL1 GCL GCL GCL GCL, GDA GCL, GDA GCL, GCS* GCL, GCS* CL1, G min. 1.0 1.0 10 1.0 1.0 2.5 1.0 1.0 1.0 1.0 1.0 1.0 typ. max. 100 100 1.0 Unit s s s ns ns s s s s s s s s s s VGH - VGL = 33 V Notes
27
HD66775
Figure 12 AC Timing
28

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